1. Field of Disclosure
Exemplary embodiments of the present invention relate to a display substrate. More particularly, exemplary embodiments of the present invention relate to a display substrate minimizing an extent of a periphery area of a display area displaying image with decline of display quality.
2. Description of Related Technology
Liquid Crystal Displays (LCD) generally include so-called, liquid crystal capacitors (CLC) formed by the counterfacing areas of respective pixel-electrodes (PE's) with corresponding portions of a common electrode where a liquid crystal material is interposed therebetween and defines a dielectric layer of the corresponding liquid crystal capacitor (CLC). However, the liquid crystal capacitor (CLC) typically does not have sufficient capacitance to store an image defining charge for a full frame period (or for another such time period until the pixel is next refreshed with new charge) and therefore it is conventional to include a so-called, storage capacitor (CST) for each pixel or pixel-electrode for assisting in the storage of a desired, image defining charge for the desired length of time.
Generally, a method for forming the at least one storage capacitor (CST) of each pixel unit includes the use of an independent wiring structure and/or the use of a previously-formed gate conductor layer. In the case of using the previously-formed gate conductor layer, the capacitance (and breakdown voltage) of the storage capacitor typically depends on a thickness of a relatively thin gate insulation layer. Therefore, the independent wiring approach is mainly used so that a breakdown voltage of the formed storage capacitor is desirably large enough to handle voltages that may be applied across the storage capacitor. One of the applied voltages typically comes from a source node disposed far away from the pixel unit. For example, in the conventional independent wiring approach, a storage voltage delivering line may be used for applying a common voltage (Vcom, as an example of an applied plate voltage) to one plate of the storage capacitor for thereby defining a charge to be stored by the storage capacitor for a predetermined retention time of the storage capacitor.
The storage voltage delivering line (also often referred to more simply as the “storage line”) has a finite conductivity and thus behaves as part of an RC delay network that undesirably slows the delivery of the desired plate voltage (e.g., Vcom) to the storage capacitor. Since, conventionally, all the storage lines are disposed to extend over their respective pixel units according to just one direction and conventionally, all these same-way extending storage lines have the desired plate voltage (e.g., Vcom) applied thereto from a centralized driving part and through a common voltage wiring, the RC delay time for applying desired plate voltage (e.g., Vcom) to the individual pixel units can vary as a function of several factors, including storage line width and distance of transmittal of the desired plate voltage (e.g., Vcom) from its source node(s).
Typically, the wiring for applying the desired plate voltage (e.g., Vcom) to the storage lines is disposed on a periphery area (PA) of the display panel (where the periphery area surrounds a display area (DA) of the display panel). On the other hand, some of the pixel units of the display area (DA) are formed deep in the interior of the display area (DA) and thus relatively far away peripheral voltage delivering wirings of the plate voltage (e.g., Vcom) applying parts of the circuit. Accordingly, when a storage capacitors driving part is switched for applying a then desired plate voltage (e.g., Vcom) to the storage capacitors, the RC delay characteristics of the storage lines comes in to play and the actual plate voltage (VP—actual) applied to the corresponding plates (e.g., storage electrodes) of the more interior pixel units is dropped, so that a display quality may be declined.
One approach to solving this problem is to have the plate voltage (e.g., Vcom) delivering wiring designed with a predetermined minimum width so that a corresponding RC factor is kept below a predetermined maximum. However, when a width of the plate voltage (e.g., Vcom) delivering wiring is increased, a ratio of the display area versus the overall panel area (DA/(DA+PA)) is undesirably decreased.
Also, when a circuit of the driving part for the plate voltage (e.g., Vcom) delivering wiring is integrated in the periphery area (PA), the periphery area (PA) needs to be extended to accommodate that driving part and once again, the ratio of the display area versus the overall panel area (DA/(DA+PA)) is undesirably decreased.
It is to be understood that this background of the technology section is intended to provide useful background for understanding the here disclosed technology and as such, the technology background section may include ideas, concepts or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to corresponding invention dates of subject matter disclosed herein.